The invention relates to a method for testing bus connections of electronic circuits, in particular memory components.
Finely structured printed circuit boards, hybrid configurations and, increasingly, multichip modules as well can be used to form highly miniaturized configurations of electronic and electrical components. A multichip module is a configuration in which a plurality of chip modules without cases or housings make contact with one another through the use of a base or carrier. In this case, chip modules are frequently used which represent large-scale-integrated, writable, electronic circuits. Such chip modules are connected at least via an address bus and a data bus to further electronic circuits, for example to processors or to chip modules of the same type. The latter case occurs in particular when the chip modules are memory modules, for example so-called RAMs. Storage elements or storage cells in the interior of a chip module can be addressed through the use of the address bus such that information which is generally binary-coded, that is to say a so-called data item, can be written via the data bus to a cell, and can be read from it. A silicon substrate or a printed circuit board, for example, may be used as the base for the at least one chip module, which in some cases may have no case. Such a construction can be accommodated in a housing or case which, as a rule, has a large number of external electrical connecting contacts which are used for data interchange.
In practice, it has been found that, when constructing finely structured configurations, faults occur in particular when making electrical contacts between a chip module (which, for example, has no case) and a base or the conductors on the base. Faults thus occur, in particular, in the soldered or bonded joints which are required in this case. On the other hand, in order to carry out a connection test, it is generally presupposed that the chip module itself and its base substrate are free of faults, since they have generally been tested separately, in advance. The faults which are possible when a contact-making connection is produced between a chip module and a base may be of different types. A first fault type is referred to as a xe2x80x9cstuck-atxe2x80x9d fault and relates to a connection like a short-circuit between an address bus line and data bus line. In this case, a so-called xe2x80x9cstuck-at 0xe2x80x9d or xe2x80x9cstuck-at 1xe2x80x9d fault relates to a connection from an address bus line or data bus line to ground or to a voltage potential. A second fault type, which is called a xe2x80x9cbridgingxe2x80x9d fault, relates to connections between more than two address bus lines or data bus lines. Finally, a third fault type is referred to as an xe2x80x9copenxe2x80x9d fault. In this case, an address bus line or data bus line has a discontinuity, such as a disconnection. A so-called xe2x80x9copen 0xe2x80x9d or xe2x80x9copen 1xe2x80x9d fault occurs depending on the nature of the line discontinuity, if the potential which occurs on the line is comparable to the level for logic zero or the level for logic one.
Such faults result in a disturbance in the data flow between an affected chip module and an electronic circuit containing this chip module. Faults in lines and contact connections on the base which are part of a data bus or address bus, that is to say the bus connections of a writable and readable integrated electronic circuit, are particularly problematic in this case. With finely structured configurations, such as a multichip module, it is thus necessary to check the connections between the base and the electronic circuit, in particular for the presence of discontinuities.
It is known, for example, for so-called xe2x80x9cin circuitxe2x80x9d tests to be used to test the connections on the surfaces of printed circuit boards. In this case, special needles or test probes are used to make external contact with selected points on the printed circuit board or with connections with electronic components located on it. This allows signals which occur during operation of the electrical circuit located on a printed circuit board to be tapped off, and to be evaluated in connected, special test apparatuses. However, owing to the small dimensions, this technique cannot be used to test, for example, multichip modules or finely structured printed circuit boards. For this reason, electronic test methods frequently have to be used for such configurations. In this case, selected bit patterns are written to input connections of an electronic circuit, which are present as standard connections and are correspondingly easily accessible. The bit patterns which occur as a reaction to this at further output connections, which are likewise present as standard and are easily accessible, can be evaluated in order to detect, in particular, short-circuits and discontinuities. A test apparatus can be connected easily, for example, if the address and data bus of an electronic circuit is accessible from outside, for example via a plug connector, or if, for example, a memory module which has no case is fitted on a base and there are easily accessible contact points for the lines of the address and data bus on the base surface.
When electronic test methods are used, a fundamental problem which occurs is that a fault on a line of the data bus of the electronic circuit to be tested can indeed be detected by writing and subsequently reading back a pattern of selected test bits. However, using this technique, it is not possible to detect a fault on a line of the associated address bus. In such a case, the test bit pattern is written to a memory cell in the electronic circuit whose address does however not match the respective predetermined address details, owing to the fault which is present. However, when read back, the test bit pattern is once again read from the same memory cell, although this is xe2x80x9cincorrectxe2x80x9d with respect to the present address details, without any address bus fault appearing to have occurred in this process.
For this reason, special test bit patterns must be used in order to also allow the detection of a fault (caused, in particular by a discontinuity) on the address bus of a writable and readable integrated electronic circuit.
The publication by C. Maxfield, entitled xe2x80x9cTesting RAMs and ROMsxe2x80x9d; EDN; Feb. 1, 1996, pages 153 to 160, discloses an electronic method for testing connections, for example of memory modules. In this case, a sequence of test bit patterns is written to the lines of the buses of a memory module, and this sequence may be referred to as a xe2x80x9cwalking-ones sequencexe2x80x9d or else a March-0/1 algorithm. In this case, each line of the external address and data buses (which generally have a width of several bits) of a memory module is stimulated once, selectively, with the logic 1 level in a rising or falling sequence, while the other lines of the address or data bus are operated at the logic 0 level. By way of example, for a data bus which has a width of four bits and has the data bits D3, D2, D1, D0, this results in the combinations 0,0,0,0; 0,0,0,1; 0,0,1,0; 0,1,0,0 and 1,0,0,0 as test bit patterns.
This method has the disadvantage that a relatively large number of write and read accesses are required in order to detect faults. For example, 64 write accesses and 64 read accesses are normally required for an 8-bit wide address bus and a 1-bit-wide data bus. A reduction to 22 may be possible, but only for the write access. Nevertheless, this still requires 86 memory accesses overall. In contrast, when using the method according to the invention, only 34 memory accesses are required in this example, that is to say 17 write accesses and 17 read accesses, in order to detect and localize possible discontinuities in the address or data bus.
A further electronic test method for the connections of, for example, memory modules is described in the publication by F. d. Jong and A. J. d. L. van Wijngaarden entitled xe2x80x9cMemory interconnect test at board levelxe2x80x9d, published in the 23rd IEEE International Test Conference; 1992; pages 328-337. This test also has the disadvantage that a relatively large number of write and read accesses are required to the cells of a memory to be tested in order to identify all the possible fault patterns which occur when there are discontinuities in the connections, and to allow the associated lines to be detected. Thus, with this electronic test method, two write accesses and one read access to the memory module are required to check each line of the address bus, that is to say each address line and, in addition, one write access and one read access to the memory module are required to check each line of the data bus, that is to say each data line. In order to cover all possible fault patterns for discontinuities in connections, this method thus also requires a considerable number of memory accesses.
The textbook by M. Gerner, B. Muller and G. Sandweg entitled xe2x80x9cSelbsttest digitaler Schaltungenxe2x80x9d [Self-test of digital circuits], R. Oldenbourg Publishers, Munich, Vienna 1990, pages 221 to 224, describes a so-called xe2x80x9cRAM self-test with deterministic test patterns.xe2x80x9d The method is based on the principle that the respective address of a memory cell is also written as a data word to the memory cell. In this case, the associated address is first of all written, in an initialization phase, word-by-word, to each memory word. This is followed by a read cycle with a nominal/actual value comparison and up to four further runs, which are referred to as phases 1 to 4. In this case, inverted and non-inverted, rising and falling address sequences are written as data values to each individual cell in the memory, are read back and are compared. The method admittedly allows a large number of fault types, which are possible in the interior of memories, to be identified, such as stuck-at faults, one-directional coupling effects and short-circuits but, on the other hand, requires a very large number of write and read memory accesses in a plurality of successive test runs.
It is accordingly an object of the invention to provide a method for testing the bus connections of writable and readable integrated electronic circuits which overcomes the above-mentioned disadvantages of the heretofore-known testing methods of this general type and which is in particular suited for testing the external connections of, for example, SRAM (static random access memory), DRAM (dynamic random access memory) or flash-memory modules which are used, for example without cases, on a printed circuit board or a multichip module.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for checking contact connections of a writable and readable integrated electronic circuit, in particular a memory component, connected to an address bus and a data bus. The method includes the steps of:
A) writing, in at least a first sequence of write steps, address bit test patterns step-by-step to an address bus, and writing data bit test patterns on a data bus into a writable and readable integrated electronic circuit;
B) writing, in at least a first sequence of read steps, the address bit test patterns again step-by-step to the address bus, and reading associated data bit patterns on the data bus from the writable and readable integrated electronic circuit;
C) comparing, in at least a first sequence of test steps, the associated data bit patterns with the data bit test patterns, in particular by pattern comparison with address and data bit fault patterns, and, in the event of discrepancies, localizing a faulty line on one of the address bus and the data bus; and
D) selecting the address bit test patterns and the data bit test patterns such that,
i) in a respective first step in one of the first sequence of write steps and read steps, bits in the address bit test pattern have a first, matching binary value,
ii) in the first step of the first sequence of write steps, bits in the data bit test pattern have a second, matching binary value, and
iii) for each following step in one of a respective sequence of write steps and read steps, starting with one of a lowest-value bit and a highest-value bit in one of the address bit test pattern and the data bit test pattern, a respective adjacent bit is assigned a respective complementary binary value with respect to a preceding step, until,
iv) in a final step in one of the respective sequence of write steps and read steps, all bits in one of the address bit test pattern and the data bit test pattern, have a binary value complementary to the first, matching binary value and the second, matching binary value, respectively.
In other words, the method according to the invention is used for checking the contact connections of a writable and readable integrated electronic circuit, in particular of a memory module, on an address bus and a data bus. In this case, in at least one first sequence of write steps, selected address bit test patterns are written step-by-step to the address bus, and selected data bit test patterns on the data bus are written to the circuit. Then, in at least one first sequence of read steps, the selected address bit test patterns are in turn written step-by-step to the address bus, and the associated data bit patterns on the data bus are read from the circuit. In at least one first sequence of test steps, the read data bit patterns are then compared with the selected data test bit patterns and, in the event of discrepancies, the faulty line on the address bus or data bus is localized, in particular by pattern comparison with address and data bit fault patterns.
According to the invention, the address and data bit test patterns are selected such that, in a first step in the first sequence of write and read steps, the bits in the address bit test pattern have a first, matching binary value, and in the first step of the first sequence of write steps, the bits in the data bit test pattern have a second, matching binary value. For each following step in the respective sequence of write and read steps, starting with the lowest-value or highest-value bit in the address or data bit test pattern, the respective adjacent bit is assigned the respective complementary binary value to the preceding step, until, in a final step in the sequence of write or read steps, all the bits in the address and data bit test patterns, respectively, have a binary value which is complementary to the respective first step.
The method according to the invention offers the advantage that it is not only possible to detect the occurrence of a fault, but also to locate the fault location precisely with a minimal number of data bit test patterns that need to be written and read back. It is thus possible to detect the respective faulty connection between a connection of the address bus or data bus of an electronic circuit and, in particular, a base substrate, for example a printed circuit board. Even if the purpose of such a method is to localize the respective faulty bit on one line of the address bus or data bus, and the nature of the fault is thus of secondary importance, the method according to the invention is thus particularly suitable for localization of the fault location of so-called xe2x80x9copen 0xe2x80x9d and xe2x80x9copen 1xe2x80x9d fault types, as well as so-called xe2x80x9cstuck-at 0xe2x80x9d and xe2x80x9cstuck-at 1xe2x80x9d faults when checking individual modules.
In accordance with another mode of the invention, in order to check the bits on the address bus and on the data bus which have a value which is greater than the value of the respective highest-value bit on the data bus or on the address bus, at least one second sequence of write, read and test steps is carried out and, in the process, selected address and data bit test patterns are written to those bits on the address or data bus, respectively, which have the greater value, and to those adjacent bits on the data or address bus, respectively, which have already had address or data bit test patterns, respectively, written to them in the first sequence of write, read and test steps, and whose number, starting with the respective lowest-value or highest-value bit in this group, corresponds to the number of bits with the greater value.
In accordance with yet a further mode of the invention, following the first sequence of write, read and test steps, a respective additional write and read and test step is carried out for the same address and data bus bits, and, in the process, at least the data bit test pattern is selected such that, in the additional write step, at least the bit in the data bit test pattern has the same binary value as that bit in the data bit test pattern whose binary value in the second write step was complementary to that in the first write step.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in method for testing the bus connections of writable and readable integrated electronic circuits, in particular of memory modules, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
The invention will be explained in more detail with reference to exemplary embodiments which are illustrated in the figures, which are described briefly below and in which: